4H-SiC MIS Capacitors and MISFETs With Deposited $\hbox {SiN}_{x}/ \hbox {SiO}_{2}$ Stack-Gate Structures

SiN_x / SiO₂ stack-gate structures, followed by N₂O annealing, have been investigated to improve the 4H-SiC metal- insulator-semiconductor (MIS) interface quality. Capacitance- voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by post- deposition annealing in N₂O at 1300degC. When the MIS capacitor with a SiN_x / SiO₂ thickness of 10 nm/50 nm was annealed in N₂O for 2 h, the interface trap density at E_c - 0.2 eV is below 1 X 10¹¹ cm ^-2eV^-1. Oxidation of SiN_x during N₂O annealing has resulted in the improvement of SiC MIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiN_x / SiO₂ stack-gate structure annealed in N₂O demonstrate a reasonably high channel mobility of 32 cm² / V ldr s on the (0001)Si face and 40 cm²/ V ldrs on the (0001) C face.