Freeze-out characterization of radiation hardened N⁺ polysilicon gate CMOS transistors

Author

Pantelakis, Dimitris C. ; Hemmenway, Donald F. ; Van vonno, Nicolaas W. ; Sanders, Thomas J.

Author_Institution

Harris Semiconductor, Melbourne, FL, USA

Volume

38

Issue

6

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1289

Lastpage

1296

Abstract

Freeze-out behavior of radiation hardened N+ polysilicon gate CMOS devices is studied at liquid-nitrogen temperature before and after irradiation at different dose levels. Explanations are given for the threshold voltage variations and freeze-out effects both before and after irradiation. The degree of freeze-out of the counterdope implant is controlled by temperature, applied gate potential, and applied body-to-source potential. Based on experimental results of this work, freeze-out is not significantly affected by irradiation doses, or the magnitude of the gate bias during radiation

Keywords

CMOS integrated circuits; radiation hardening (electronics); 77 K; body-to-source potential; counterdope implant; degree of freeze-out; experimental results; freeze-out characterization; freeze-out effects; gate bias during radiation; gate potential; irradiation doses; polycrystalline Si gate transistors; polysilicon gate CMOS transistors; radiation hardened CMOS; temperature effects; threshold voltage variations; CMOS process; CMOS technology; Circuits; Cryogenics; Doping; Implants; Impurities; Radiation hardening; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.124107

Filename

124107

Freeze-out characterization of radiation hardened N+ polysilicon gate CMOS transistors

Pantelakis, Dimitris C. ; Hemmenway, Donald F. ; Van vonno, Nicolaas W. ; Sanders, Thomas J.

jour

Freeze-out characterization of radiation hardened N⁺ polysilicon gate CMOS transistors