Analysis of logarithmic number system processors

Author

Stouraitis, Thanos ; Taylor, Fred J.

Author_Institution

Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA

Volume

35

Issue

5

fYear

1988

fDate

5/1/1988 12:00:00 AM

Firstpage

519

Lastpage

527

Abstract

An analysis of a logarithmic number system (LNS) processor is presented. The analysis includes processor designs that overcome the historical limitation of the word-length of LNS, thus increasing the precision of the processor. A 20-bit LNS VLSI chip layout and timing estimates have been produced in cooperation with Honeywell Inc. Using an enhanced 1.25-ns technology, and inserting pipelining registers in the addition/subtraction data path, a 24-bit adaptive radix processor (ARP)/LNS processor can be realized. The predicted performance of the device would be on the order of 20 ns for multiplication/division and 40 ns for addition/subtraction. This class of processors is now supported with a predictive error model. The theoretical studies were supported and verified by computer simulation experiments at all levels of analysis

Keywords

computerised signal processing; digital arithmetic; microprocessor chips; 1.25 micron; 20 bit; 20 ns; 24 bit; 40 ns; DSP; Honeywell; LNS; VLSI chip layout; adaptive radix processor; computer simulation experiments; error analysis; logarithmic number system processors; performance; pipelining registers; predictive error model; timing estimates; Adaptive systems; Arithmetic; Digital filters; Digital signal processing; Error analysis; Helium; Logic; Quantization; Roundoff errors; Signal processing;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.1779

Filename

1779