• DocumentCode
    816884
  • Title

    A 1 K shadow RAM for circumvention applications

  • Author

    Murray, James R.

  • Author_Institution
    Sandia Nat. Lab., Albuquerque, NM, USA
  • Volume
    38
  • Issue
    6
  • fYear
    1991
  • fDate
    12/1/1991 12:00:00 AM
  • Firstpage
    1403
  • Lastpage
    1409
  • Abstract
    A method for creating a circumvention memory using existing technologies is presented. Since no single memory technology can meet all the requirements, two memory cells (CMOS and SNOS) were combined in a shadow RAM configuration. The resulting circuit has been characterized to verify that performance goals were achieved
  • Keywords
    MOS integrated circuits; SRAM chips; radiation hardening (electronics); 1 kbit; CMOS/SNOS; circumvention applications; circumvention memory; existing technologies; shadow RAM configuration; two memory cells; CMOS technology; Circuits; Iron; Laboratories; Nonvolatile memory; Radiation hardening; Random access memory; Read-write memory; Silicon; Writing;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.124124
  • Filename
    124124
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=816884