Title :
A 1 K shadow RAM for circumvention applications
Author :
Murray, James R.
Author_Institution :
Sandia Nat. Lab., Albuquerque, NM, USA
fDate :
12/1/1991 12:00:00 AM
Abstract :
A method for creating a circumvention memory using existing technologies is presented. Since no single memory technology can meet all the requirements, two memory cells (CMOS and SNOS) were combined in a shadow RAM configuration. The resulting circuit has been characterized to verify that performance goals were achieved
Keywords :
MOS integrated circuits; SRAM chips; radiation hardening (electronics); 1 kbit; CMOS/SNOS; circumvention applications; circumvention memory; existing technologies; shadow RAM configuration; two memory cells; CMOS technology; Circuits; Iron; Laboratories; Nonvolatile memory; Radiation hardening; Random access memory; Read-write memory; Silicon; Writing;
Journal_Title :
Nuclear Science, IEEE Transactions on
