The effect of temperature on single-particle latchup

Author

Johnston, A.H. ; Hughlock, B.W. ; Baze, M.P. ; Plaag, R.E.

Author_Institution

Boeing Def. & Space Group, Seattle, WA, USA

Volume

38

Issue

6

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1435

Lastpage

1441

Abstract

Special test structures fabricated with three different CMOS processes were used to investigate the effect of elevated temperature on single-particle latchup. The latchup threshold was strongly affected by contact geometry, and its temperature dependence is consistent with a model based on triggering of the vertical parasitic transistor. Threshold LET values decreased by about a factor of 2.5 at 125°C relative to room temperature values for all three processes. Saturation cross sections exceeded the isolation well area for the two bulk processes because of diffused charge. Laser studies showed that latchup could be triggered by strikes outside the isolation well, consistent with the diffused charge mechanism. These same mechanisms were consistent with measurements of the latchup cross section of a static CMOS RAM

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit testing; ion beam effects; 125 degC; 25 degC; CMOS processes; contact geometry; diffused charge; heavy ion tests; isolation well area; latchup threshold; model; saturation cross sections; single-particle latchup; static CMOS RAM; temperature dependence; test structures; threshold LET; vertical parasitic transistor triggering; CMOS process; CMOS technology; Doping profiles; Laser modes; Predictive models; Space technology; Substrates; Temperature dependence; Temperature distribution; Testing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.124129

Filename

124129