Title :
SEU-hardened resistive-load static RAMs
Author :
Massengill, Lloyd W.
Author_Institution :
Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA
fDate :
12/1/1991 12:00:00 AM
Abstract :
A charge partitioning (CP) design technique for MOS resistive-load static RAMs (RMOS SRAMs) is presented. This technique, when applied to RMOS SRAMs with specific capacitance attributes, may produce significant SEU error-rate control without sacrifices in area or power consumption. Silicon-on-insulator (SOI) technology, usually not considered appropriate for conventional RMOS SRAMs because of reduced storage capacitances, appears to be an excellent technology for CP-hardened RMOS. Simulated CP-hardened, 4-transistor RMOS RAM cells in SOI approach the error-rate performance of rad-hard, full 6-transistor CMOS cells
Keywords :
MOS integrated circuits; SRAM chips; integrated circuit testing; radiation hardening (electronics); semiconductor-insulator boundaries; 4-transistor RMOS RAM cells; MOS resistive-load static RAMs; RMOS SRAMs; SEU; SOI technology; capacitance attributes; charge partitioning design technique; error-rate control; error-rate performance; Analytical models; CMOS technology; Capacitance; Circuit simulation; Feedback; Random access memory; Read-write memory; Resistors; Silicon on insulator technology; Voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
