Title :
A 2-ns detecting time, 2-μm CMOS built-in current sensing circuit
Author :
Shen, Tung-Li ; Daly, James C. ; Lo, Jien-Chung
Author_Institution :
United Microelectronics Corp., Hsinchu City, Taiwan
fDate :
1/1/1993 12:00:00 AM
Abstract :
Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns
Keywords :
CMOS integrated circuits; VLSI; built-in self test; electric sensing devices; fault location; integrated circuit testing; 2 micron; 2 ns; 30 MHz; CMOS VLSI; MOSIS; SPICE3 simulations; built-in current sensing circuit; defect coverage; implanted open-circuit defects; implanted short-circuit defects; p-well CMOS technology; parallel multiplier; power bus current; CMOS technology; Circuit synthesis; Circuit testing; Circuits; Clocks; Delay effects; Diodes; Intrusion detection; MOS devices; Microelectronics; Monitoring; P-n junctions; Sampling methods; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
