Title :
CRRES microelectronic test chip
Author :
Lin, Y.S. ; Buehler, M.G. ; Ray, K.P. ; Sokoloski, M.M.
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fDate :
12/1/1991 12:00:00 AM
Abstract :
The JPL CRRES chip was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three orders of magnitude smaller than would be estimated from Co-60 ground tests. Unshielded (outer board) MOSFETs have a threshold-voltage damage factor that would be estimated from Co-60 ground tests. Temperature swings as large as 23°C with a 22.5 orbit periodicity affected the MOSFET data and were removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix, thus reducing the complexity and mass of the experiment
Keywords :
carrier mobility; field effect integrated circuits; insulated gate field effect transistors; integrated circuit testing; radiation effects; shielding; 60Co ground tests; CRRES MEP; JPL CRRES chip; channel mobility degradation; matrix results; microelectronic test chip; orbit periodicity; radiation effects; radiation-induced MOSFET threshold voltage shifts; shielded MOSFETs; shielding; threshold-voltage damage factor; unshielded MOSFETs; Circuit testing; Ionizing radiation; Laboratories; MOSFET circuits; Microelectronics; Radiation effects; Space technology; Temperature sensors; Threshold voltage; Very large scale integration;
Journal_Title :
Nuclear Science, IEEE Transactions on
