Complementary pass-transistor energy recovery logic for low-power applications

In the paper, a low-power adiabatic logic called complementary pass-transistor energy recovery logic (CPERL) is proposed. It utilises the bootstrapping technique to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. A single CPERL gate requires only one phase power clock. The energy dissipation between CPERL and other logic circuits is compared by simulation. Simulation results show that a CPERL 10-stage inverter chain only consumes 48.8% of energy dissipated in conventional CMOS at 125 MHz. The operation of an 8-bit CPERL carry lookahead adder designed using the TSMC 0.35 μm 1P4M CMOS technology has been verified. Therefore, system-on-chip (SoC) and portable computing applications can be realised using CPERL circuits