Characterization and modeling of parasitic emission in deep submicron CMOS

Author

Vrignon, Bertrand ; Bendhia, Sonia Delmas ; Lamoureux, Enrique ; Sicard, Etienne

Author_Institution

Central Res. & Dev., STMicroelectronics, Crolles, France

Volume

47

Issue

2

fYear

2005

fDate

5/1/2005 12:00:00 AM

Firstpage

382

Lastpage

387

Abstract

This paper presents a study of the parasitic emissions of a 0.18-μm CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.

Keywords

CMOS integrated circuits; electromagnetic interference; integrated circuit noise; interference suppression; lumped parameter networks; switching; CMOS experimental integrated circuit; EMI; complementary metal-oxide semiconductor; conducted noise measurements; deep submicron CMOS; electromagnetic interference; emission reduction techniques; internal current switching; lumped-element model; parasitic emission; CMOS integrated circuits; Electromagnetic interference; Electromagnetic modeling; Integrated circuit modeling; Noise measurement; Packaging; Predictive models; Semiconductor device modeling; Switching circuits; Testing; Complementary metal–oxide semiconductor (CMOS) technology; electromagnetic compatability (EMC); electromagnetic interference (EMI) modeling; on-chip sampling;

fLanguage

English

Journal_Title

Electromagnetic Compatibility, IEEE Transactions on

Publisher

ieee

ISSN

0018-9375

Type

jour

DOI

10.1109/TEMC.2005.847408

Filename

1433064