Title :
A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS
Author :
Maitra, Kingsuk ; Misra, Veena
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.
Keywords :
CMOS integrated circuits; MOSFET; ion implantation; leakage currents; quantum interference phenomena; semiconductor device metallisation; semiconductor device models; work function; 25 nm; 25 nm bulk CMOS; NMOS devices; PMOS devices; bandedge workfunction metal gates; bulk MOSFETs; drain induced barrier lowering; full device simulations; linear chain of inverters; midgap gates; midgap workfunction metal gates; off-state leakage specification; on state drive current; pocket halo implants; polysilicon gates; process integration; quantum effects; short channel effects; simulation; stage delay; CMOS process; CMOS technology; Delay effects; Delay lines; Doping profiles; Implants; Inverters; MOS devices; MOSFETs;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.819267