Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS

This work argues that the foremost challenges to the continued rapid improvements in CMOS integrated circuit (IC) performance are power consumption and design robustness. Furthermore, these two goals are often contradictory in nature, which indicates that joint optimization approaches must be adopted to properly handle both. To highlight needs in computer-aided design (CAD), we review a sampling of state-of-the-art work in power reduction techniques, and also in the newly emerging area of statistical optimization applied to very large scale integration (VLSI) ICs. The lack of CAD techniques to perform multiobjective function optimization (specifically parametric yield under correlated performance metrics) is a major limitation of current CAD research. In addition, with design trends pushing towards architectures based on aggressive adaptivity and voltage scaling, CAD researchers and engineers will need to refocus efforts on enabling this type of complex design