Investigation of multi-bit upsets in a 150 nm technology SRAM device

Multi-bit upset (MBU) events collected from accelerated soft error rate (SER) measurements performed with a quasi-monoenergetic neutron beam were analyzed with a threefold purpose. The first goal was to qualitatively assess the applicability and effectiveness of single-bit Error Detection And Correction algorithms and circuits (EDAC). The second goal was to investigate the relationship with the memory core P-well tapping scheme. And the third goal was to identify "preferred" MBU shapes. The results showed that the memory architecture is critical in affecting the single-bit EDAC effectiveness. Also, it was put in evidence that the tapping scheme is very effective in reducing the MBU rate. And finally it was noted that the predominant MBU shape is strongly influenced by the vertical and horizontal distance of the active nodes of the memory cells.