Asymmetric SEU in SOI SRAMs

Author

McMarr, P.J. ; Nelson, M.E. ; Liu, S.T. ; Nelson, D. ; Delikat, K.J. ; Gouker, P. ; Tyrrell, B. ; Hughes, H.

Author_Institution

U.S. Naval Res. Lab., Washington, DC, USA

Volume

52

Issue

6

fYear

2005

Firstpage

2481

Lastpage

2486

Abstract

Partially depleted (PD) 0.15 μm CMOS silicon-on-insulator (SOI) SRAMs were exposed to heavy ions, 14 MeV neutrons, and protons. The upset threshold and saturated cross section LET values were determined from heavy ion exposures. The SRAMs were then exposed at various angles of incidence with respect to a 14 MeV neutron source to a total fluence of 4×10¹³ n/cm². The number of upsets from front exposure was more than double the number from back exposure. Following neutron exposure, proton upset measurements were performed. For a given fluence, the number of proton induced upsets was essentially identical to the number of neutron induced upsets.

Keywords

CMOS integrated circuits; SRAM chips; neutron effects; proton effects; silicon-on-insulator; CMOS silicon-on-insulator SRAM; LET values; SOI SRAM; heavy ions; neutron effect; neutron source; proton induced upsets; Cyclotrons; Laboratories; Neutrons; Performance evaluation; Protons; Random access memory; Silicon on insulator technology; Single event upset; Space technology; Testing; Random access memories; silicon-on-insulator technology; single event upset;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2005.860720

Filename

1589227