HBD using cascode-Voltage switch logic gates for SET tolerant digital designs

Author

Casey, M.C. ; Bhuva, B.L. ; Black, J.D. ; Massengill, L.W.

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN, USA

Volume

52

Issue

6

fYear

2005

Firstpage

2510

Lastpage

2515

Abstract

Cascode-voltage-switch logic family of gates is evaluated for single-event vulnerability. As the data is stored on two storage nodes for each logic gate in this logic family, as opposed to only one for static logic family, the single-event transient pulse does not propagate for more than a few stages. Simulation results show single-event transient pulse termination after one logic gate. Area, speed, and power requirements for cascode-voltage logic are comparable to that of static logic.

Keywords

CMOS logic circuits; MIS devices; digital storage; hardness; logic design; logic gates; radiation hardening (electronics); cascode-voltage switch logic gates; complementary metal-oxide-semiconductor; digital circuit; hardness-by-design; logic design; radiation hardening; single event transistor pulse; storage nodes; tolerant digital design; CMOS logic circuits; Digital circuits; Frequency; Logic design; Logic devices; Logic gates; Pulse circuits; Radiation hardening; Senior members; Switches; Complementary metal–oxide–semiconductor (CMOS); digital circuits; logic design; radiation hardening; single-event;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2005.860715

Filename

1589231