Title :
Single-event mitigation in combinational logic using targeted data path hardening
Author :
Srinivasan, V. ; Sternberg, A.L. ; Duncan, A.R. ; Robinson, W.H. ; Bhuva, B.L. ; Massengill, L.W.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA
Abstract :
A technique is proposed to selectively harden complex combinational logic circuits to single-event (SE) upsets. Propagation paths with sensitive nodes are identified and hardened while minimizing impact on circuit performance.
Keywords :
combinational circuits; logic circuits; radiation hardening (electronics); arithmetic logic unit; combinational logic circuits; harden complex circuits; radiation-hardening; sensitive nodes; single-event mitigation; single-event upsets; soft errors; targeted data path hardening; Arithmetic; Circuit optimization; Combinational circuits; Cranes; Error analysis; Frequency; Logic; Manufacturing processes; Redundancy; Signal generators; Arithmetic Logic Unit (ALU); combinational logic; radiation-hardening; soft errors;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2005.860714
