RHBD techniques for mitigating effects of single-event hits using guard-gates

Author

Balasubramanian, A. ; Bhuva, B.L. ; Black, J.D. ; Massengill, L.W.

Author_Institution

Electr. Eng. Dept., Vanderbilt Univ., Nashville, TN, USA

Volume

52

Issue

6

fYear

2005

Firstpage

2531

Lastpage

2535

Abstract

Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hits are presented. Simulation results show that the designs using guard-gates are less susceptible to single-event hits. Area, power, and speed penalty for guard-gate designs for combinational logic are found to be minimal. For latches, the area penalty is higher but speed penalty is minimal.

Keywords

CMOS digital integrated circuits; circuit simulation; combinational circuits; logic design; radiation hardening (electronics); RHBD techniques; addressing combinational logic hits; complementary metal-oxide-semiconductor; guard-gates; hardening-by-design techniques; mitigating effects; single-event hits; single-event transients; storage cell hits; transient pulsewidth; Circuit synthesis; Clocks; Combinational circuits; Error analysis; Frequency; Latches; Logic design; Pulse circuits; Pulse generation; Voting; Complementary metal–oxide–semiconductor (CMOS); single-event hits; single-event transient (SET); transient pulsewidth;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2005.860719

Filename

1589234