DocumentCode :
819053
Title :
SEU performance of TAG based flip-flops
Author :
Shuler, R.L. ; Kouba, C. ; Neill, P. M O
Author_Institution :
Avionic Syst. Div., NASA Johnson Space Center, Houston, TX, USA
Volume :
52
Issue :
6
fYear :
2005
Firstpage :
2550
Lastpage :
2553
Abstract :
We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 μ process.
Keywords :
flip-flops; ion beam effects; logic design; logic gates; dual rail synchronous designs; heavy-ion test; single rail asynchronous designs; single-event upset; tolerant latch based flip-flops; transition NAND gates; Circuits; Delay; FETs; Flip-flops; Inverters; Latches; Rails; Single event upset; Technical Activities Guide -TAG; Voting; Single-event effects; soft errors;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2005.860712
Filename :
1589237
Link To Document :
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