Title :
Low power adiabatic programmable logic array with APDL-2
Author :
Yang, W.J. ; Zhou, Y. ; Lau, K.T.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Abstract :
A novel low power programmable logic array (PLA) structure based on adiabatic switching is presented. Simulation results show that the power consumption is similar to that of the adiabatic pseudo-domino logic (APDL) PLA, but while standard transistor sizing for the isolation transistor can be applied, in APDL PLA this transistor was designed with a larger width.
Keywords :
CMOS logic circuits; low-power electronics; programmable logic arrays; APDL-2; adiabatic pseudo-domino logic circuit structure; adiabatic switching; low power PLA structure; low power programmable logic array; power consumption; standard sized isolation transistor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030994
