Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels

This brief presents the design and implementation of a clock-and-data recovery (CDR) design for low-voltage differential signals (LVDS) transceiver operations. Instead of using an oversampling scheme which requires a high-speed clock generator, we adopt an interpolation scheme which relaxes the demand of a high-speed phase-locked loop with very high precision. A dual-tracking design is proposed to precisely align both edges of a data eye. Hence, the center of a data eye can be optimally sampled. A standard foundry 0.25-mum 1P5M CMOS technology is used to realize the proposed dual-tracking CDR for 7times100 (bit-MHz) LVDS signaling. The post-layout-extracted simulation reveals that the worst-case jitter of the sampling clocks is less than 450 ps (peak-to-peak) and 250 ps (rms) at all process corners