Title :
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns
Author :
Bongjin Kim ; Injae Yoo ; In-Cheol Park
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.
Keywords :
Long Term Evolution; interleaved codes; turbo codes; Long Term Evolution turbo codes; arithmetic relationship; block size; hardware complexity; low complexity parallel QPP interleaver; parallel interleaved addresses; parallel interleaving; parallel turbo decoder; permutation patterns; quadratic permutation polynomial interleaver; Complexity theory; Decoding; Hardware; Logic gates; Memory management; Multiprocessor interconnection; Turbo codes; Parallel architecture; permutation pattern (PP); quadratic permutation polynomial (QPP) interleaver; turbo decoder;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2013.2240911