Video data format converters using minimum number of registers

Author

Parhi, Keshab K.

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

2

Issue

2

fYear

1992

fDate

6/1/1992 12:00:00 AM

Firstpage

255

Lastpage

267

Abstract

The implementation of video data format using a minimum number of registers is considered. A systematic lifetime analysis of the variables is carried out to determine the latency and the minimum number of registers needed for the converter. The technique of obtaining the minimum number of registers is illustrated using four classes of data format converters: line-by-line to column-by-column, line-by-line to interleaved skewed one-dimensional block format, line-by-line to interleaved two-dimensional block format, and line-by-line to zigzag format. Closed-form expressions for minimum number of registers in these converters are obtained in terms of the number of input and output pixels processed per cycle and the number of input and output bits processed per pixel in a cycle

Keywords

convertors; shift registers; video equipment; closed form expressions; image processing; input bits; input pixels; interleaved skewed 1D block format; interleaved two-dimensional block format; lifetime analysis; line by line converter; output bits; output pixels; registers; video data format converters; zigzag format; Clocks; Closed-form solution; Data conversion; Delay; Image converters; Pixel; Random access memory; Read-write memory; Registers; Silicon;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.143424

Filename

143424