Title :
Efficient FPGA implementation of bit-stream multipliers
Author :
Ng, C.W. ; Wong, N. ; Ng, T.S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Hong Kong
Abstract :
A four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables
Keywords :
adders; field programmable gate arrays; multiplying circuits; sigma-delta modulation; FPGA implementation; adder circuits; field programmable gate array; four-input adder structure; sigma-delta bit-stream multiplier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20070293
