Title :
Area-efficient high-speed 3D DW processor architecture
Author :
Jiang, M. ; Crookes, D.
Author_Institution :
Sch. of Electron., Queen´´s Univ. Belfast
Abstract :
An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128times128times128 fMRI volume image in 20 ms
Keywords :
digital arithmetic; discrete wavelet transforms; field programmable gate arrays; hardware description languages; image processing; microprocessor chips; 3D discrete wavelet transform; VHDL; Xilinx Virtex-E FPGA; distributed arithmetic; fMRI image; five-level DWT analysis; high-speed 3D DWT processor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20070201
