Title :
An efficient output phase assignment for PLA minimization
Author :
Wey, Chin-Long ; Chang, Tsin-Yuan
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
fDate :
1/1/1990 12:00:00 AM
Abstract :
When a multiple-output function is realized by a PLA (programmable logic array), there is often the option of realizing either true or complementary logic for each output. The tradeoffs in implementing PLAs with and without output phase assignment are explored, and an efficient output phase assignment for PLA minimization is presented. The results of this study show that the proposed algorithm reduces the number of product terms by as much as 50% when the output phase assignment is considered
Keywords :
logic arrays; logic design; minimisation of switching nets; PLA minimization; complementary logic; logic design; multiple-output function; output phase assignment; product terms; programmable logic array; time logic; Boolean functions; Design automation; Logic arrays; Logic design; MOS devices; Minimization methods; NP-complete problem; Programmable logic arrays; Pulse inverters;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
