A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP₃) of 0.03 dBm, and second-order input intercept point (IIP₂) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.