Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL

The authors present an integrated computer-aided design environment, the VAR (VHDL-based array reconfiguration) system, for the tasks of design, reconfiguration, simulation, and evaluation in an architecture modeled by VHDL. An easily diagnosable and reconfigurable two-dimensional defect-tolerant processing element (PE) switch lattice array is used as an example to illustrate the methodology of VAR. VAR allows the designers study and evaluate fault diagnosis and reconfiguration algorithms by inserting faults, which are generated based on manufacturing yield data, into the array and then locating the fault PEs as well as simulating the reconfiguration process. Thus, VAR can assist the designers in evaluating the different combinations of fault patterns, fault diagnosis algorithms, and reconfigurable architectures through a complete set of figures of merit which aim at architectural improvements. Extensive simulation and evaluation have been performed to demonstrate and support the effectiveness of VAR