DocumentCode :
822212
Title :
Investigation of dielectric/metal bilayer sidewall diffusion barrier for Cu/porous ultra-low-k interconnects
Author :
Chen, Zhe ; Prasad, Krishnamachar ; Li, Chaoyong ; Jiang, Ning ; Gui, Dong
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume :
5
Issue :
1
fYear :
2005
fDate :
3/1/2005 12:00:00 AM
Firstpage :
133
Lastpage :
141
Abstract :
A dielectric/metal bilayer structure of a-SiC:H/Ta was integrated and investigated for application as a sidewall diffusion barrier in a Cu/porous ultra-low-k interconnect structure. Different dielectric/metal bilayer thicknesses were investigated. The electrical tests and physical analyses indicate that this a-SiC:H/Ta bilayer structure is a more efficient sidewall diffusion barrier than the conventional physical vapor deposited (PVD) multistack TaN/Ta metal barrier. With a similar total sidewall barrier thickness, an even better barrier integrity and reliability can be achieved by using a thicker a-SiC:H layer and a correspondingly thinner Ta barrier. This achievement is mostly attributed to the surface modification and sealing of the porous ultra-low-k surface by the a-SiC:H layer. Thus, the scenario of the barrier failure due to defects in the Ta (or TaN) barrier layer directly deposited on rough porous ultra-low-k material is avoided. Bias-temperature stress (BTS) and time-to-failure (TTF) studies indicate the Copper penetration through the sidewall barrier into the porous dielectric was the dominating failure mechanism in the conventional PVD TaN/Ta barrier and bilayer barrier of thinner a-SiC:H (14 Å) and thicker Ta (71 Å) layers, although the latter enhanced the lifetime of interconnect structures considerably. The bilayer barrier consisting of a thicker a-SiC:H (60 Å) and correspondingly thinner Ta (53 Å) layers was more robust to protect the sidewall region so that this sidewall Cu diffusion induced failure mechanism was no longer found in Cu/porous ultra-low-k interconnect structures even after thermal stress at 200°C for 120 h.
Keywords :
copper; dielectric materials; diffusion barriers; integrated circuit interconnections; reliability; silicon compounds; tantalum; Cu; SiC:H-Ta; TaN; bias-temperature stress; dielectric/metal bilayer sidewall diffusion barrier; physical vapor deposited multistack metal barrier; porous ultra-low-k interconnects; reliability; rough porous ultra-low-k material; time-to-failure study; Atherosclerosis; Copper; Dielectric materials; Failure analysis; Protection; Robustness; Rough surfaces; Surface roughness; Testing; Thermal stresses; Cu damascene interconnects; a-SiC:H; diffusion barrier; porous ultra-low-; pseudobreakdown; time-to-failure;
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2005.843833
Filename :
1435397
Link To Document :
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