DocumentCode :
822288
Title :
Effect of CMOS technology scaling on thermal management during burn-in
Author :
Semenov, Oleg ; Vassighi, Arman ; Sachdev, Manoj ; Keshavarzi, Ali ; Hawkins, C.F.
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Waterloo, Ont., Canada
Volume :
16
Issue :
4
fYear :
2003
Firstpage :
686
Lastpage :
695
Abstract :
Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss during burn-in. The authors estimate the increase in junction temperature with technology scaling. Their research shows that under normal operating conditions, the junction temperature is increasing 1.45×/generation. The increase in junction temperature under the burn-in condition was found to be exponential. The range of optimal burn-in voltage and temperature is reduced significantly with technology scaling.
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; leakage currents; thermal management (packaging); thermal resistance; Arrhenius model; CMOS technology scaling; IC technology scaling; junction temperature; optimal burn-in temperature; optimal burn-in voltage; optimal stressed temperature; optimization procedure; quality improvement; thermal management; thermal resistance models; thermal runaway; time-dependent dielectric breakdown models; voltage acceleration factor models; yield loss; CMOS logic circuits; CMOS technology; Clocks; Frequency; Integrated circuit technology; Leakage current; Microprocessors; Technology management; Temperature; Thermal management;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2003.818985
Filename :
1243983
Link To Document :
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