DocumentCode :
822389
Title :
Test compaction for sequential circuits
Author :
Niermann, Thomas M. ; Roy, Rabindra K. ; Patel, Janak H. ; Abraham, Jacob A.
Author_Institution :
Sunrise Test Syst., Los Altos, CA, USA
Volume :
11
Issue :
2
fYear :
1992
fDate :
2/1/1992 12:00:00 AM
Firstpage :
260
Lastpage :
267
Abstract :
The authors describe a number of heuristic algorithms to compact a set of test sequences generated by a sequential circuit automatic test pattern generator (ATPG). A model has been developed and analyzed which shows that finding the optimal solution has an exponential worst-case complexity. To achieve an acceptable run time, some heuristics have been developed that yield good suboptimal solutions in a very short time. Three heuristic algorithms were developed. These algorithms were implemented in C and lex and applied to several of the ISCAS-89 benchmark sequential circuits. They reduce the test length by 17%-63% with a very small time overhead, while having little effect on the original fault overage
Keywords :
automatic testing; logic testing; sequential circuits; C implementation; automatic test pattern generator; heuristic algorithms; lex implementation; model; optimal solution; sequential circuits; test sequences; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Compaction; Heuristic algorithms; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.124404
Filename :
124404
Link To Document :
بازگشت