• DocumentCode
    822738
  • Title

    IDDQ test: will it survive the DSM challenge?

  • Author

    Sabade, Sagar S. ; Walker, D.M.H.

  • Author_Institution
    Texas A&M Univ., TX, USA
  • Volume
    19
  • Issue
    5
  • fYear
    2002
  • Firstpage
    8
  • Lastpage
    16
  • Abstract
    Deep-submicron technologies pose difficult challenges for IDDQ testing in the future. The low threshold voltage used by DSM devices decreases the defect resolution of IDDQ. However, because IDDQ is a valuable test method, researchers are working to augment with other test parameters to prolong its effectiveness
  • Keywords
    CMOS integrated circuits; integrated circuit testing; leakage currents; CMOS circuits; DSM devices; deep-submicron devices; direct drain quiescent current testing; integrated circuit testing; leakage current; spatial correlation; Breakdown voltage; Circuit faults; Circuit testing; Current measurement; Face detection; Leakage current; Semiconductor device measurement; Semiconductor device testing; Subthreshold current; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2002.1033787
  • Filename
    1033787
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=822738