• DocumentCode
    822793
  • Title

    High defect coverage with low-power test sequences in a BIST environment

  • Author

    Girard, Patrick ; Landrault, Christian ; Pravossoudovitch, Serge ; Virazel, Arnaud ; Wunderlich, Hans-Joachim

  • Author_Institution
    Microelectron. Dept., LIRMM, Montpellier, France
  • Volume
    19
  • Issue
    5
  • fYear
    2002
  • Firstpage
    44
  • Lastpage
    52
  • Abstract
    A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact
  • Keywords
    built-in self test; design for testability; logic testing; BIST; DFT; built-in self-test; digital circuits; parallel BIST implementation; random single-input change; test generation; test pattern sequence; Built-in self-test; Circuit faults; Circuit testing; Delay; Digital circuits; Electrical fault detection; Fault detection; Random number generation; Robustness; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2002.1033791
  • Filename
    1033791
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=822793