DocumentCode
822973
Title
Fast floating-point normalisation unit realised using NOR planes
Author
Han, Kyung-Nam ; Han, Sang-Wook ; Yoon, Euisik
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Volume
38
Issue
16
fYear
2002
fDate
8/1/2002 12:00:00 AM
Firstpage
857
Lastpage
858
Abstract
A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns
Keywords
CMOS logic circuits; NOR circuits; counting circuits; floating point arithmetic; normalising; 0.18 micron; 1.4 ns; 64 bit; CMOS; LZC; NOR planes; control signals; floating-point normalisation unit; leading zero counter; normalisation shifter; shift decoder;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020555
Filename
1033808
Link To Document