Title :
Reduced clock swing domino logic
Author_Institution :
Dept. of Electron., Politecnico di Torino, Italy
fDate :
8/1/2002 12:00:00 AM
Abstract :
A reduced clock swing domino logic gate for 50% reduction in power consumption in clock networks is presented. The original full swing gate works properly at reduced swing with a better noise tolerance and small loss of performance while simple resizing allows the same speed, power and noise figures
Keywords :
clocks; integrated circuit noise; logic gates; clock swing; domino logic gate; noise figure; noise tolerance; power consumption; resizing method;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020632
