DocumentCode :
823103
Title :
Optimized synthesis techniques for testable sequential circuits
Author :
Eschermann, Bernhard ; Wunderlich, Hans-Joachim
Author_Institution :
Inst. fuer Rechnerentwurf und Fehlertoleranz, Karslruhe Univ., Germany
Volume :
11
Issue :
3
fYear :
1992
fDate :
3/1/1992 12:00:00 AM
Firstpage :
301
Lastpage :
312
Abstract :
The authors describe a synthesis approach that maps a behavioral finite state machine (FSM) description into a testable gate-level structure. The term testable, besides implying the existence of tests, also means that the application of test patterns is facilitated. Depending on the test strategy, the state registers of the FSM are modified, e.g. as scan path or self-test registers. The additional functionality of these state registers is utilized in system mode by interpreting them as smart state registers, capable of producing certain state transitions on their own. To make the best use of such registers, the authors propose a novel state encoding strategy based on an analytic formulation of the coding constraint satisfaction problem as a quadratic assignment problem. An additional minimization potential can be exploited by appropriately choosing the pattern generator for self-testable designs. Experimental results indicate that, compared with conventional design for testability approaches, significant savings are possible this way
Keywords :
circuit CAD; encoding; logic CAD; logic testing; sequential circuits; CAD; FSM; behavioral finite state machine; coding constraint satisfaction problem; minimization potential; optimised synthesis techniques; pattern generator; quadratic assignment problem; self-testable designs; smart state registers; state encoding strategy; state transitions; system mode; test patterns; testable gate-level structure; testable sequential circuits; Automata; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Encoding; Minimization; Registers; Sequential analysis; Sequential circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.124417
Filename :
124417
Link To Document :
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