Efficient Multiternary Digit Adder Design in CNTFET Technology

Author

Sridharan, K. ; Gurindagunta, S. ; Pudi, Vikramkumar

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai, India

Volume

12

Issue

3

fYear

2013

fDate

May-13

Firstpage

283

Lastpage

287

Abstract

This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79% reduction in power-delay product for three-trit adders and 88 % reduction in power-delay product for nine-trit adders in comparison to a direct realization.

Keywords

adders; carbon nanotube field effect transistors; decoding; encoding; logic design; CNTFET technology; carbon nanotube field effect transistor technology; decoder blocks; encoder blocks; extensive HSPICE simulation; low-complexity encoder; multiternary digit adder design; multitrit adder; power-delay product reduction; reduced complexity carry-generation unit; single-trit full-adder design; Adders; CNTFETs; Carbon nanotubes; Complexity theory; Decoding; Delay; Logic gates; Carbon nanotube field effect transistor (CNTFET); multiternary digit adder; power-delay product; ternary digit (Trit);

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2013.2251350

Filename

6475189