Title :
Planarization of dielectric layers for multilevel metallization
Author :
Riley, Paul E. ; Castel, Egil D.
Author_Institution :
Schlumberger Palo Alto Res., CA, USA
fDate :
11/1/1988 12:00:00 AM
Abstract :
A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO2 films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO2 must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF4/O2 high pressure plasma generated in a low radio-frequency etching system
Keywords :
CVD coatings; dielectric thin films; integrated circuit technology; metallisation; silicon compounds; sputter etching; 0.2 micron; Ar/CF4/O2 high pressure plasma; LPCVD; SiO2; abrupt topography; chemical-vapor deposition; dielectric layers; fine line ICs; low pressure CVD; low radio-frequency etching system; multilevel metallization; pillar interconnections; plasma etching; response-surface methodology; sacrificial photoresist; Chemical processes; Dielectrics; Etching; Integrated circuit interconnections; Integrated circuit metallization; Planarization; Plasma applications; Plasma measurements; Resists; Surfaces;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
