Channel/switchbox definition for VLSI building-block layout

A study is made of the problem of routing region definition and ordering in VLSI building-block layout design. An algorithm to decompose the routing area into straight channels and rectangular switchboxes corresponding to line segments in the routing structure of the placement such that the number of switchboxes is minimized, is presented. The algorithm is based on a graph-theory approach that makes use of an efficient polynomial time algorithm for computing minimum clique covers of triangulated graphs. Experimental results indicate that the algorithm performs well. For all the test problems considered, the algorithm consistently outperformed a previous known greedy algorithm, and it produced optimal solutions in all but one case