Title :
High-speed, address-encoding arbiter architecture
Author :
Georgiou, J. ; Andreou, A.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
Abstract :
An address-encoding arbiter architecture is presented that is suitable for large asynchronous circuits requiring address event representation readout. It provides improvement in power and speed, while also reducing area. By encoding the address in each layer of the arbiter tree, the address line loads are distributed throughout the tree, thus reducing the maximum single load on a line driver.
Keywords :
asynchronous circuits; driver circuits; integrated circuit design; logic design; readout electronics; tree codes; address event representation readout; address line loads; address-encoding arbiter architecture; arbiter tree; asynchronous circuits; line driver;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20063914
