• DocumentCode
    824827
  • Title

    High-speed, address-encoding arbiter architecture

  • Author

    Georgiou, J. ; Andreou, A.G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
  • Volume
    42
  • Issue
    3
  • fYear
    2006
  • Firstpage
    170
  • Lastpage
    171
  • Abstract
    An address-encoding arbiter architecture is presented that is suitable for large asynchronous circuits requiring address event representation readout. It provides improvement in power and speed, while also reducing area. By encoding the address in each layer of the arbiter tree, the address line loads are distributed throughout the tree, thus reducing the maximum single load on a line driver.
  • Keywords
    asynchronous circuits; driver circuits; integrated circuit design; logic design; readout electronics; tree codes; address event representation readout; address line loads; address-encoding arbiter architecture; arbiter tree; asynchronous circuits; line driver;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20063914
  • Filename
    1593309
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=824827