Title :
A versatile dual-mode transposition latch array design for DCT in HDTV applications
Author :
Dejhan, K. ; Cheevasuvit, F. ; Trisuwannawat, T. ; Kaneko, M.
Author_Institution :
Fac. of Eng., King Mongkut´´s Inst. of Technol. Ladkrabang, Bangkok, Thailand
fDate :
11/1/1992 12:00:00 AM
Abstract :
A latch-based dual-mode matrix transposer memory for discrete cosine transform (DCT) data format conversion in HDTV applications is described. 1.2-μm double-metal HCMOS3 technology is used. The static latch cell is 19.7 μm×24.5 μm excluding a pass-transistor multiplexer. By using this technology, the DCT runs at a rate up to 27 megapixels per second. The dimension of the matrix depends on the number of memory points. The memory cell uses the static shift latch with minimum area and power dissipation
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; discrete cosine transforms; high definition television; 1.2 micron; DCT data format conversion; HDTV applications; VLSI; area; discrete cosine transform; double-metal HCMOS3 technology; latch-based dual-mode matrix transposer memory; memory cell; number of memory points; pass-transistor multiplexer; power dissipation; static latch cell; static shift latch; Assembly; Circuits; Design engineering; Discrete cosine transforms; HDTV; Latches; Matrix converters; Power engineering and energy; Registers; Signal processing;
Journal_Title :
Consumer Electronics, IEEE Transactions on
