Title :
Modulo 2n±1 adder design using select-prefix blocks
Author :
Efstathiou, Costas ; Vergos, Haridimos T. ; Nikolos, Dimitris
Author_Institution :
Dept. of Informatics, TEI, Athens, Greece
Abstract :
We present new design methods for modulo 2n±1 adders. We use the same select-prefix addition block for both modulo 2n-1 and diminished-one modulo 2n+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.
Keywords :
CMOS logic circuits; VLSI; adders; carry logic; logic design; logic gates; VLSI architectures; carry computation; computer arithmetic; logic gates; modulo 2n±1 adders; select-prefix blocks; static CMOS; Adders; Circuits; Computer architecture; Concurrent computing; Costs; Cryptography; Design methodology; Digital arithmetic; TCPIP; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2003.1244938
