Title :
On synthesis of easily testable (k, K) circuits
Author :
Naidu, Srinath R. ; Chandru, Vijay
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
Abstract :
A (k, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.
Keywords :
Boolean functions; combinational circuits; computational complexity; fault diagnosis; logic design; logic gates; logic testing; trees (mathematics); Boolean expression; circuit synthesis; circuit testing; combinational circuit; k-tree; polynomial time complexity; stuck-at fault; treewidth; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Logic functions; Logic testing; Polynomials; Signal synthesis;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2003.1244946