DocumentCode :
824965
Title :
Single-fault fault-collapsing analysis in sequential logic circuits
Author :
Chen, Jwu E. ; Lee, Chung Len ; Shen, Wen Zen
Author_Institution :
Dept. of Electr. Eng., China Coll. of Eng., Hsinchu, Taiwan
Volume :
10
Issue :
12
fYear :
1991
fDate :
12/1/1991 12:00:00 AM
Firstpage :
1559
Lastpage :
1568
Abstract :
A study is made of single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults
Keywords :
automatic testing; circuit analysis computing; fault location; logic testing; sequential circuits; delayed reconvergence; feedback paths; prime fan-out branches; self-hiding; sequential logic circuits; single-fault fault collapsing; storage elements; Benchmark testing; Circuit analysis; Circuit faults; Circuit testing; Combinational circuits; Delay; Fault diagnosis; Feedback; Logic circuits; Sequential circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.103505
Filename :
103505
Link To Document :
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