DocumentCode :
824978
Title :
A state assignment procedure for single-block implementation of state charts
Author :
Drusinsky-Yoresh, Doron
Author_Institution :
Sony Corp., Kanagawa, Japan
Volume :
10
Issue :
12
fYear :
1991
fDate :
12/1/1991 12:00:00 AM
Firstpage :
1569
Lastpage :
1576
Abstract :
The authors presents a simple, single-block implementation scheme for state charts which uses a single conventional combinational-logic block and a state register. The most attractive feature of the proposed scheme is the absence of communication. It eliminates the need for communicating FSMs (finite state machines) owing to an older realization method, and does so without having to account for all state configurations implied by concurrency. The author investigates the state encoding conditions for the implementation and suggests an appropriate optimization technique
Keywords :
logic CAD; optimisation; state assignment; combinational-logic block; optimization technique; single-block implementation; state assignment procedure; state charts; state encoding conditions; state register; Automata; Communication system control; Concurrent computing; Design automation; Encoding; Hardware; Rivers; Specification languages; Sufficient conditions; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.103506
Filename :
103506
Link To Document :
بازگشت