DocumentCode
825044
Title
Radiation-Hard CMOS/SOS Standard Cell Circuits
Author
Palkuti, Leslie J. ; Pryor, Richard
Author_Institution
Naval Research Laboratory Washington, D. C. 20375
Volume
23
Issue
6
fYear
1976
Firstpage
1715
Lastpage
1719
Abstract
A new multiport silicon-gate, CMOS/SOS standard cell family that achieves transient upset and total dose hardness has been designed and evaluated. This radiation hardness was achieved by design and process procedures normally not considered in conventional CMOS/SOS circuits. To evaluate the cell family a test chip and arithmetic logic unit (ALU) integrated circuits were fabricated. The cell-family performance was characterized utilizing 60ns to l¿s electron pulses from the LINAC and total dose gamma irradiation from the cobalt-60 source. The results show circuit upset at levels greater than 1011 rad (Si)/s for short (60ns) irradiation pulses. Total dose irradiations to 106 rad (Si) indicate a 20 percent reduction in circuit speed and a factor of 10 increase in chip leakage. Utilizing these standard cell building blocks, radiation hard, quick-turnaround, low-cost custom LSI arrays can be fabricated using design automation techniques.
Keywords
Arithmetic; CMOS logic circuits; CMOS process; Circuit testing; Electrons; Integrated circuit testing; Linear particle accelerator; Logic circuits; Logic testing; Process design;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.1976.4328567
Filename
4328567
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