Intersignal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling

Intersignal timing skew gives rise to reduced timing margins at receivers and limits the data rate of parallel links. This paper proposes a new intersignal timing-skew-compensation technique for parallel links with voltage-mode incremental signaling. The proposed technique employs an early/late block to detect the rising and falling edges of the pulses generated by intersignal timing skews at the far end of channels and, subsequently, allocates the optimal sampling point of the sampler of each data bit to maximize the timing margins. Two cascaded delay-locked loops (DLLs) are employed to place the sampling clock to the optimal sampling position of each data bit. The skew-compensation ranges are determined from the delay ranges of the DLLs. The effectiveness of the proposed deskewing method is validated using a parallel link with data rate of 1 GB/s and four microstrip channels on an FR4 substrate. The data link is implemented in UMC-0.13-mum 1.2-V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. Simulation results are presented.