Title :
How RISCy is DSP?
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
The characteristics of benchmark digital signal processing (DSP) algorithms are examined. These characteristics are used to suggest the features of an ideal DSP architecture, which is compared to current DSP and reduced instruction set computer (RISC) architectures. Timing comparisons taken from data books and research show that several on-the-market RISCs have a DSP performance close to or better than some DSP chips. Analysis of these DSP and RISC architectures leads to the suggestion of an ideal low-cost RISC DSP chip.<>
Keywords :
digital signal processing chips; reduced instruction set computing; signal processing; DSP architecture; DSP performance; RISC DSP chip; RISC architectures; RISCs; benchmark; Algorithm design and analysis; Digital signal processing; Digital signal processing chips; Finite impulse response filter; Performance analysis; Pursuit algorithms; Reduced instruction set computing; Silicon; Sparks; Timing;
Journal_Title :
Micro, IEEE
