Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

Author

Mansuri, Mozhgan ; Liu, Dean ; Yang, Chih-Kong Ken

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

37

Issue

10

fYear

2002

fDate

10/1/2002 12:00:00 AM

Firstpage

1331

Lastpage

1334

Abstract

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8× the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-μm CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8·FO-4)] and 1.5 GHz [=1/(6.7·FO-4)] for two techniques, respectively, whereas a conventional PFD operates at <1 GHz [=1/(10·FO-4)]. The two proposed PFDs achieve a capture range of 1.7× and 1.4× the conventional design, respectively.

Keywords

CMOS digital integrated circuits; detector circuits; digital phase locked loops; high-speed integrated circuits; timing circuits; 0.25 micron; 1.25 GHz; 1.5 GHz; CMOS process; GSamples/s PLL; clock generator; fast frequency acquisition; latch-based PFD architecture; pass-transistor DFF PFD architecture; phase-frequency detectors; phase-locked loop; Circuits; Clocks; Delay; Inverters; Phase detection; Phase frequency detector; Phase locked loops; Prototypes; Voltage; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.803048

Filename

1035948