Novel analogue VLSI design for multilayer networks

The authors introduce a new pulse-stream analogue VLSI design which has been optimised for the implementation of multilayer networks. The requirements of fully-trained multilayer perceptrons have been analysed to produce a set of specifications for the hardware design. The pulse-stream circuits described in the paper are driven from a fixed-frequency master clock, and a synaptic multiply-and-add computation is performed with every pulse. Detailed SPICE simulations have been carried out, and preliminary results from a set of test chips are also presented