DocumentCode :
828438
Title :
Schedulability analysis and optimisation for the synthesis of multi-cluster distributed embedded systems
Author :
Pop, P. ; Eles, P. ; Peng, Z.
Volume :
150
Issue :
5
fYear :
2003
Abstract :
An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches
Keywords :
embedded systems <synthesis of multi-cluster distrib. embedded systs., schedulability anal. and optim.>; heuristic programming <synthesis of multi-cluster distrib. embedded systs., schedulability anal. and optim.>; optimisation <synthesis of multi-cluster distrib. embedded systs., schedulability anal. and optim.>; processor scheduling <synthesis of multi-cluster distrib. embedded systs., schedulability anal. and optim.>; queueing theory <synthesis of multi-cluster distrib. embedded systs., schedulability anal. and optim.>; workstation clusters <synthesis of multi-cluster distrib. embedded systs., schedulability anal. and optim.>; buffer size; bus access parameters; event-triggered clusters; inter-cluster traffic routing; minimal buffer needs; multicluster distributed embedded system synthesis; optimisation heuristics; priority assignment; schedulability analysis; schedulability optimisation; time-triggered clusters; worst case queuing delay analysis;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:20030829
Filename :
1245599
Link To Document :
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